As will be appreciated by those skilled in the art, most semiconductor devices have several layers of circuits interconnected by vias etched through insulating and/or dielectric materials separating the two levels of circuits and filled with a conductive material such copper, gold, silver or aluminum. To avoid electrical shorts, it is very important that these vias filled with conductive metals do not unintentionally come into contact with other conductive lines and/or devices. Since electrical circuits and devices in an integrated chip are very small, a via that does successfully connect two levels of circuits together, but is misaligned by only a few tenths of microns may cause shorts and render a full wafer of devices useless. As will be appreciated by those skilled in the art, most misaligned vias are the result of a misaligned etching mask. Therefore, it is important that precautions be taken to be sure minor misalignment will not cause shorts. Perhaps the most common way to avoid such destructive electrical shorts is to increase the area that is allocated for the via etch. That is, increase the separation between circuits, or electrical conductive lines, and the location where the via is etched from an upper level to a lower level. This is, of course, a simple and effective solution. Unfortunately, since each of such multi-layer devices will typically include several vias, and since each wafer includes hundreds of devices, increasing the area for each via is also wasteful and decreases yield.
Therefore, it would be advantageous if misalignment of the etch mask could be avoided so that the area allocated for each via could be reduced.